李晓维：1964年9月出生于安徽省肥西县；现任计算机体系结构国家重点实验室常务副主任、中科院计算所学位评定委员会副主席。李晓维于1985和1988年分别获得合肥工业大学计算机系学士和硕士学位、1991年获中科院计算所博士学位。1993年任北京大学计算机系副教授；2000年任中科院计算所研究员；2013年入选国家百千万人才工程并获“有突出贡献中青年专家”荣誉称号；入选2014年“科技北京”百名领军人才培养工程。

　　2000年以来主要研究领域为VLSI测试、容错计算。先后主持国家自然科学基金重点项目2项、973课题2项、863项目2项、北京市科技重点项目1项、XX预研项目1项；合作出版专著4本；在包括ISCA/HPCA/DSN/DAC/ICCAD等IEEE国际学术会议、IEEE/ACM Transactions等国际学术刊物、中国科学/JCST等国内学术刊物上合作发表学术论文200余篇（其中SCI收录50余篇）；授权发明专利50余件、软件著作权登记50余项。先后获得中国科学院自然科学奖（1992年度）、杰出科技成就奖（CPU团队/2003年度）、教学成果奖（2008年度）；获得中国计算机学会王选奖（2008年度）、中国质量学会质量技术奖（2011年度）；北京市科学技术奖（2007年度和2008年度）；国家技术发明奖（2012年度）。

　　现任中国计算机学会常务理事、容错计算专业委员会主任；Journal of Computer Science and Technology (JCST）副主编；Journal of Electronic Testing: Theory and Applications (JETTA) 和Journal of Low Power Electronics (JOLPE）编委；IEEE Asia and Pacific Regional TTTC Vice-Chair；IEEE ATS Steering Committee Chair（2011-2013）；IEEE WRTLT Steering Committee Chair（2008-2010）；担任IEEE ITC/VTS/DATE等国际学术会议程序委员会委员。　　

部分学术著作:

(1) 李晓维, 吕涛, 李华伟, 李光辉 著《数字集成电路设计验证: 量化评估, 激励生成, 形式化验证》, 科学出版社, 2010年5月, 411页

(2) 李晓维, 韩银和, 胡瑜, 李佳 著《数字集成电路测试优化: 测试压缩, 测试功耗优化, 测试调度》, 科学出版社, 2010年6月, 344页

(3) 李晓维, 胡瑜, 张磊, 鄢贵海 著《数字集成电路容错设计: 容缺陷/故障, 容参数偏差, 容软错误》, 科学出版社, 2011年4月, 433页

部分期刊论文:

[1] Y. Fang, H. Li, Xiaowei Li, “Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications”, IEEE Transactions on VLSI Systems, Vol.22, No.5, May 2014, pp.1450-1455

[2] J. Ye, Y. Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, and Huaxing Tang, “Diagnose Failures Caused by Multiple Locations At-a-Time”, IEEE Transactions on VLSI Systems, Vol.22, No.4, April 2014, pp.824-837

[3] K. Huang, Y. Hu, Xiaowei Li, “A Reliability-Oriented Placement and Routing Algorithm for SRAM-based FPGAs”, IEEE Transactions on VLSI Systems, Vol.22, No.2, Feb 2014, pp.256-269

[4] B. Fu, Y. Han, H. Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels”, IEEE Transactions on VLSI Systems, Vol.22, No.1, Jan 2014, pp.113-126

[5] Y. Zhang, H. Li, Xiaowei Li, “Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded Processors”, IEEE Transactions on VLSI Systems, Vol.21, No.7, July 2013, pp.1220-1233

[6] Z. He, T. Lv, H. Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures under Statistical Timing Model”, IEEE Transactions on VLSI Systems, Vol.21, No.7, July 2013, pp.1210-1219

[7] S. Jin, Y. Han, H. Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction”, IEEE Transactions on VLSI Systems, Vol.21, No.5, May 2013, pp.821-833

[8] Y. Chen, L. Zhang, Y. Han, Xiaowei Li, “Thermal-Constrained Scheduling for Interconnect Energy Reduction in 3D Homogeneous MPSoCs”, IEEE Transactions on VLSI Systems, Vol.21, No.2, Feb. 2013, pp.239-249

[9] S. Pei, H. Li, Xiaowei Li, “Flip-flop Selection for Partial Enhanced Scan to Reduce Transition Test Pattern Volume”, IEEE Transactions on VLSI Systems, Vol.20, No.12, Dec. 2012, pp.2157-2169

[10] S. Pei, H. Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture”, IEEE Transactions on VLSI Systems, Vol.20, No.09, Sept 2012, pp.1565-1577

[11] S. Pan, Y. Hu, Xiaowei Li, “IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults”, IEEE Transactions on VLSI Systems, Vol.20, No.05, May 2012, pp.777-790

[12] X. Fu, H. Li, Xiaowei Li, “Testable Path Selection and Grouping for Faster Than At-Speed Testing”, IEEE Transactions on VLSI Systems, Vol.20, No.02, February 2012, pp.236-247

[13] M. Zhang, H. Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects”, IEEE Transactions on VLSI Systems, Vol.19, No.11, November 2011, pp.1969-1982

[14] Y. Zhang, H. Li, Y. Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects”, IEEE Transactions on VLSI Systems, Vol.19, No.10, October 2011, pp.1787-1800

[15] G. Yan, Y. Han, Xiaowei Li, “SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation”, IEEE Transactions on VLSI Systems, Vol.19, No.9, September 2011, pp.1627-1640

[16] G. Yan, Y. Han, Xiaowei Li, “ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation”, IEEE Transactions on Computers, Volume 60, Issue 9, September 2011, pp.1219-1232

[17] D. Fan, Xiaowei Li, G. Li, “New Methodologies for Parallel Architecture”, Journal of Computer Science and Technology, 26(4): 578-584, July 2011

[18] G. Yan, Y. Han, H. Liu, X. Liang, Xiaowei Li, “Microfix: Using timing interpolation and delay sensors for power reduction”, ACM Transactions on Design Automation of Electronic Systems, March 2011, Vol. 16, No. 2, Article 16:1-21

[19] Z. An, H. Zhu, C. Xu, Y. Xu, Xiaowei Li, “Synchronization of Linear Pulse-coupled Oscillators with Different Frequency”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2205-2215

[20] Y. Yang, Y. Xu, Xiaowei Li, “A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2126-2137

[21] J. Li, Q. Xu, Y. Hu, Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture- Power Reduction in At-Speed Scan-Based Testing”, IEEE Transactions on VLSI Systems, Vol.18, No.7, July. 2010, pp.1081-1092

[22] L. Zhang, Y. Han, Q. Xu, Xiaowei Li, H. Li, “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on VLSI Systems, Vol.17, No.9, Sept. 2009, pp.1173-1186

[23] Y. Han, Y. Hu, Xiaowei Li, A. Chandra, Huawei Li, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI Systems, Vol.15, No.5, May 2007, pp.531-540

主持的部分项目：

[1] 973课题“大规模高通量计算系统的可靠性设计”(2011CB302503)；

[2] 973课题“高性能处理芯片的可靠性设计”(2005CB321604)；

[3] NSFC重点项目“数字VLSI电路测试技术研究”(60633060)；

[4] NSFC重点项目“从行为级到版图级的设计验证与测试生成”(60207002)；

[5] NSFC项目“微处理器自修复设计基础技术研究”(90707004)；

[6] NSFC与RGC联合资助项目“片上系统测试架构设计与优化：针对噪声引起的测试良产率下降的研究”(60831160526)；

[7] 863项目“大规模高可靠片上多处理器的系统结构及实现方法”(2007AA01Z113)；

[8] 863项目“软硬件协同的低功耗系统设计”(2001AA111070)；

[9] 北京市科技重点课题“IC设计验证/测试关键技术研发与实用”(H020120140130)；

[10] XX预研项目“软件可靠性测试基础技术” (41315050102)；