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导师介绍
姓名 张磊  性别 男 
联系方式 zlei@ict.ac.cn  职称 正高级工程师 
研究方向 计算机系统,嵌入式芯片,智能物联网AIoT 
个人介绍
简历:
  张磊,博士生导师,教授级工程师,计算所学术百星,中科院青促会成员。2003年在成都电子科技大学计算机系获学士学位,2008年在中科院计算所获博士学位,2012-2013年在美国伊利诺伊理工和芝加哥大学任高级研究助理。张磊博士目前是物端计算系统实验室执行副主任,面向万物智联和边缘计算开展前瞻性研究工作,发表过多篇CCF A类期刊会议论文,承担着中科院、基金委、科技委等多个重点项目。张磊团队在国内最早参与并推动开源指令系统RISC-V,先后成功完成基于RISC-V指令集的物端AI芯片一代、二代的设计和流片,数量级提升目前嵌入式和单片机的能力。2018年,张磊与前Intel中国研究院首席科学家王元陶研究员共同创办科技公司中科物栖(jeejio.com),获得了中科院科技成果转化特等奖。张磊博士入选了2019年《财富》杂志评选的40位40岁以下商业精英以及全球创始人峰会“最具行业影响力创始人”。
研究方向:
计算机系统,嵌入式芯片,智能物联网AIoT
社会任职:
 
获奖及荣誉:
2011年,中国质量协会质量技术奖,一等奖
2017年,北京市科学技术奖,二等奖
2019年,中科院科技成果转化奖,特等奖
代表论著:
[1] L. Chao, X. Peng, Z. Xu, L. Zhang, “Ecosystem of Things: Hardware, Software, and Architecture”, Proceedings of the IEEE, 107(8), 2019. (CCF A)
[2] Y. Wang, Y. Han, L. Zhang, H. Li, X. Li, "ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Computing", ACM/IEEE 52nd Design Automation Conference (DAC), 47-52, July, 2015. (CCF A)
[3] JB. Dong, L. Zhang, YH. Han, Y. Wang, XW. Li, "Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation", ACM/IEEE 48th Design Automation Conference (DAC), 972-977, Aug. 2011. (CCF A)
[4] Y. Wang, Y. Han, H. Li, L. Zhang, Y. Cheng, X. Li, "PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 24 (5), pp. 1613-1625, 2016. 
[5] Y. Wang, L. Zhang, Y. Han, H. Li, X. Li, "Data Remapping for Static NUCA in Degradable Chip Multiprocessors", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(5), pp. 879-892, May, 2015. 
[6] Y. Wang, YH. Han, L. Zhang, BZ. Fu, C. Liu, HW. Li, XW. Li, "Economizing TSV Resources in 3-D Network-on-Chip Design", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(3), 493-506, March, 2015. 
[7] Y. Wang, L. Zhang, YH. Han, HW. Li, "Reinventing Memory System Design for Many-Accelerator Architecture", Journal of Computer Science and Technology (JCST), 29 (2), 273-280, Mar. 2014.
[8] P. Chen, L. Zhang, YH. Han, YJ. Chen, "A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications", Journal of Computer Science and Technology (JCST), 29 (2), 239-246, , Mar. 2014.
[9] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 21(2), 239-249, Feb. 2013.
[10] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "TSV Minimization for Circuit-Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), 28 (1): 119-128, Jan. 2013.
[11] ZW. Xu, XH. Peng, L. Zhang, D. Li, NH. Sun, "The Φ-Stack for Smart Web of Things", ACM/IEEE Symposium on Edge Computing(SEC), 2017.
[12] Y. Wang, L. Zhang, YH. Han, HW. Li, XW. Li, "Flex Memory: Exploiting and Managing Abundant Off-chip Optical Bandwidth", ACM/IEEE Design, Automation and Test in Europe (DATE), 1-6, May 2011. (CCF B)
[13] C. Liu, L. Zhang, YH. Han, XW. Li, "A Resilient On-Chip Router Design Through Data Path Salvaging", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.
[14] C. Liu, L. Zhang, YH. Han, XW. Li, "Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.
[15] WW. Chen, Y. Wang, S. Yang, L. Zhang, C. Liu, "You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design", IEEE/ACM Proceedings of Design, Automation and Test in Europe (DATE), 2020.
[16] L. Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), pp.1173-1186, Sep. 2009.
[17] L. Zhang, Y. Yu, J. Dong, Y. Han, S. Ren, X. Li. "Performance-Asymmetry-Aware Topology Virtualization for Defect-Tolerant NoC-based Many-core Processors", IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 1566-1571, Dresden, Germany, March 8-12, 2010.
[18] L. Zhang, Y. Han, Q. Xu and X. Li. "Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology", IEEE/ACM Design, Automation and Test in Europe (DATE), pp: 891-896, Munich Germany, March 10-14, 2008.
承担科研项目情况:
1、国家自然科学基金项目:基于片上网络的众核处理器容错设计方法研究(负责人)
2、国家自然科学基金项目:高效能自适应处理器体系结构关键技术研究(负责人)
3、计算所创新课题:可重塑处理器原理与关键技术研究(负责人)
4、计算所创新课题:物端计算机(负责人)
学科类别:
计算机系统结构
所属部门:
泛在计算系统研究中心
专家类别:
正高
杰青入选时间:
百人入选时间:
其他备注:
博导计算机系统结构
其他备注2:
 
其他备注3:
 
 
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