Name: Chengyong Wu  Education: Ph.D 
Positions:   Academic title: Professor 
E-mail: cwu@.ict.ac.cn 
Personal Website:  
Chengyong Wu received a B.S. degree in Mathematics from Fudan University in 1991, a M.S. in Computer Engineering from Beihang University in 1996, and a Ph.D in Computer Sciences from the Institute of Computing Technology, Chinese Academy of Sciences, in 2000. He then joined ICT as a researcher working on compiler technology and became Full Professor in 2006. His research spans instruction-level parallelizing compilation, parallel programming model and language, and iterative and adaptive optimization. He received CVIC Software Fund Talents Award at 2003 and has served as PC member of several international conferences like HiPEAC ‘10, ICPP ‘04, and ACSAC ’04, ’05, ‘07, etc. He is a member of ACM, and a senior member of CCF.

Compiler optimization, parallel programming model 
Community service:

1. Yang Chen, Yuanjie Huang, Lieven Eeckhout, Grigori Fursin, Liang Peng, Olivier Temam, Chengyong Wu, Evaluating Iterative Optimization Across 1000 Data Sets, ACM SIGPLAN 2010 Conference on Programming Language Design and Implementation (PLDI 2010), June 5 - 10, 2010, Toronto, Canada.
2. Lianjie Luo, Yang Chen, Chengyong Wu, Shun Long, Grigori Fursin, Finding representative sets of optimizations for adaptive multiversioning applications, 3rd Workshop on Statistical and Machine Learning Approaches to Architectures and Compilation (SMART ’09), January 25, 2009, Paphos, Cyprus.
3. Yang Chen, Bin Fan, Lujie Zhong, Chengyong Wu, Diva: A Dataflow Programming Model and its Runtime Support in Java Virtual Machine, Proceedings of The 13th Asia-Pacific Computer Systems Architecture Conference (ACSAC ’08), August 4 - 6, 2008. Hsinchu, Taiwan.
4. Lei Liu, Li Chen, Chengyong Wu, Xiaobing Feng, Global loop tiling for distributed memory systems, 14th International Euro-Par Conference European Conference on Parallel and Distributed Computing (Euro-Par 2008), Vol. 5168, 2008.
5. Bin Bao, Chengyong Wu, Zhaoqing Zhang, Reducing Code Size Through Storage Assignment for Restricted Indexed Addressing Mode, The 4th Workshop on Optimizations for DSP and Embedded Systems (ODES-4), March 26, 2006. Manhattan, NY.
6. Feng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang, A Register Allocation Framework for Banked Register Files with Access Constraints, Proceedings of The 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC ’05), Singapore, October 24 - 26, 2005. Lecture Notes in Computer Science, Springer, Vol. 3740, pp. 269-280.
7. Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Roy Ju, Optimizing Packet Accesses for a Domain Specific Language on Network Processors, Proceedings of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC ’05), Hawthorne, New York, October 20-22, 2005.
8. Chengyong Wu, Ruiqi Lian, Junchao Zhang, Roy Ju, Sun Chan, Lixia Liu, Xiaobing Feng, Zhaoqing Zhang, An Overview of the Open Research Compiler, Post-Proceedings of The 17th International Workshop on Languages and Compilers for Parallel Computing (LCPC ’04), Lecture Notes in Computer Science, Springer, Vol. 3602, pp. 17-31, 2005.
9. Dong-Yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu, Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. J. Instruction-Level Parallelism, 2004, vol.6.
10. Dong-Yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Ju, Efficient Resource Management during Instruction Scheduling for the EPIC Architecture, Efficient Resource Management During Instruction Scheduling for the EPIC Architecture. Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT ’03), Oct. 2003. Pages 36 – 45.

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